The present invention relates generally to digital arithmetic logic units, and more specifically to a fast ALU=0 circuit for use with carry-select lookahead adders.
In many digital computers, a determination must often be made of whether the output of the ALU is equal to zero. If this must be done in the general case, the ALU=0 determination must be made based on the actual outputs of the ALU calculation. This result will often then be used to compute the result of a condition test. Since the ALU=0 determination cannot be made until after the ALU computation is completed, and further processing must then be done on this value, the ALU=0 computation is involved in the critical timing path for the computer.
In high speed applications, such as a microprocessor operating at more than 20 MHz, reducing delay in the critical timing path is extremely important. When gate delays are on the order of a few nanoseconds, an unecessary delay of 2 or 3 gate periods is critical. If a microprocessor is designed to operate at 40 MHz, the clock period is 25 nanoseconds. 3 gate delays of 2 nanoseconds each repreents nearly 25% of the total clock period.
It is therefore an object of the present invention to provide an ALU=0 computation circuit which minimizes the delay beyond the actual ALU computation itself. It is a further object to provide such minimum delay computation in connection with the use of a carry-select lookahead ALU.
Therefore, according to the present invention, a circuit for computing whether the result of an ALU computation is zero determines whether certain bits are zero before the ALU computation is complete. When the final ALU computation is available, only a very small number of bits need be considered to determine whether the result is zero. This determination is made with the insertion of only 1 additional gate delay after the ALU computation is complete.